Presentation Details
| Mechanisms of Hysteresis in Cd(Se, Te) Photovoltaic Devices Marco Nardone1, Collin J.Deweese1, Bryson C.Byers1, Greg Spurgin1, Zachary I.Flood1, Alli Daly1, B.Edward Sartor2, Eric Colegrove2, Matthew O.Reese2. 1Bowling Green State University, Bowling Green, OH, USA.2National Laboratory of the Rockies, Golden, CO, USA |
Abstract
Hysteresis and metastability continue to limit the interpretability and long-term optimization of high-efficiency Cd(Se,Te) thin-film photovoltaic devices. Despite widespread observations of reversible performance changes under illumination, bias, and thermal stress, the underlying physical mechanisms remain unresolved. Here, we investigate hysteresis in As-doped Cd(Se,Te) solar cells using a combined experimental and numerical modeling approach aimed at identifying transport-level origins rather than phenomenological trends. Devices exhibit substantial increases in open-circuit voltage (Voc) and fill factor following light–heat treatment at open-circuit bias, with minimal changes in short-circuit current, quantum efficiency, or doping, suggesting that metastability may not be governed by bulk transport effects. Temperature-dependent JV analysis reveals a pronounced increase in the Voc activation energy after charge injection, indicating a transition from interface-dominated recombination pathways to bulk recombination. Finite-element device simulations reproduce the observed hysteresis by modifying front-interface properties, particularly the conduction band offset and the density and charge state of interface defects. These results suggest that hysteresis arises from bias-induced evolution of interface energetics and recombination mechanisms at the absorber/buffer junction. More broadly, the findings underscore the need to explicitly account for defect kinetics, interface charge, and tunneling-assisted transport in both experiments and device models. Establishing predictive links between charge injection, interface modification, and recombination physics will be critical for stabilizing performance, improving voltage margins, and guiding interface engineering strategies in next-generation Cd(Se,Te) photovoltaic technologies.
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No part of this publication may be reproduced, distributed, or transmitted in any form or by any means, including photocopying, recording, or other electronic or mechanical methods, without the prior written permission of the author.