Presentation Details
| Experimental signatures of light and voltage bias-induced hysteresis in Cd(Se, Te) devices B.Edward Sartor1, Marco Nardone2, Chun-Sheng Jiang1, Steve Johnston1, Craig L.Perkins1, Ryan Muzzio1, Joshua Brown1, Eric Colegrove1, Matthew O.Reese1. 1National Laboratory of the Rockies, Golden, CO, USA.2Bowling Green State University, Bowling Green, OH, USA |
Abstract
Both legacy and contemporary Cd(Se,Te) devices demonstrate a performance hysteresis modulated by heat and applied light or voltage bias history. A robust understanding of the nature of this hysteresis has eluded researchers in recent years. In this work, a suite of characterization techniques is applied to two research cell architectures with varied Se content at the front interface to understand the origin of this effect. Results suggest that in devices with high initial Se segregation, bias reduces the effect of trap-mediated mobility, decreasing fill factor. Additionally, during light or forward voltage bias, a field develops at the front interface of both devices which reduces the magnitude of the cliff-like conduction band offset, further improving voltage and fill-factor. The region driving the light-hysteresis effect is isolated to the front and quasi-front interface, indicating areas of future investigation to the CdTe community.
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No part of this publication may be reproduced, distributed, or transmitted in any form or by any means, including photocopying, recording, or other electronic or mechanical methods, without the prior written permission of the author.
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